The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, in IC manufacturing, it is typical that via (or plug) holes are etched through a low-k dielectric layer in order to make connections for interconnect structures. Across a wafer, the via holes may be distributed unevenly, with some areas of the wafer having dense via patterns and some areas having isolated via patterns. This creates a so-called “pattern loading effect” in the via etching process, causing some via holes to be over-etched and some via holes to be under-etched. To counter this problem, a traditional approach deposits a silicon-based etch stop layer between the low-k dielectric layer and the layer underneath. Ideally, all of the via holes should land at the silicon-based etch stop layer. However, as the semiconductor processes continue scaling down, this traditional silicon-based etch stop layer is no longer sufficient in certain cases. For example, conductor line widths may have a wider range in new designs and via holes may have a higher aspect ratio in new processes. As a result, the traditional silicon-based etch stop layer may not effectively prevent via hole over-etching and under-etching issues. Improvements in this area are desired.